The Sparse Polyhedral Framework: Composing Compiler-Generated Inspector-Executor Code

An approach for code generation in the Sparse Polyhedral Framework

Applications that manipulate sparse data structures contain memory reference patterns that are unknown at compile time due to indirect accesses such as A[B[i]]. To exploit parallelism and improve locality in such applications, prior work has developed a number of run-time reordering transformations (RTRTs). This paper presents the Sparse Polyhedral Framework (SPF) for specifying RTRTs and compo...

Computer Science Technical Report Enabling Code Generation within the Sparse Polyhedral Framework

Loop transformation frameworks based on the polyhedral model use libraries such as Polylib, ISL, and Omega to represent and manipulate polyhedra and use tools like CLooG to generate loops that scan the modified polyhedra. Most of these libraries are restricted to iteration space sets and memory/array access functions with affine constraints that preclude the specification of run-time reordering...

A New Optimization Technique for the Inspector-Executor Method

This paper presents our HPF compiler using our modified inspector-executor method for implementing accesses to a distributed array. In our modified method, a compiler runs an inspector during compile time to obtain the information of data dependency among node processors, and it uses that information to optimize communication code included in the executor. This paper presents our idea, performa...

An Approach for Proving the Correctness of Inspector/Executor Transformations

To take advantage of multicore parallelism, programmers and compilers rewrite, or transform, programs to expose loop-level parallelism. Showing the correctness, or legality, of such program transformations enables their incorporation into compilers. However, the correctness of inspector/executor strategies, which develop parallel schedules at runtime for computations with nonaffine array access...

Automatic Parallelizing Compiler for Distributed Memory Parallel Computers: New Algorithms to Improve the Performance of the Inspector/executor